blob: 52df22ab3f6aeb9cc4d59a5f49c7b0e7e508960f [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
};
cluster1 {
core0 {
cpu = <&CPU2>;
};
core1 {
cpu = <&CPU3>;
};
};
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <130>;
exit-latency-us = <80>;
min-residency-us = <300>;
};
};
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2-kryo-cpu";
nvmem-cells = <&speedbin_efuse>;
opp-shared;
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2-kryo-cpu";
nvmem-cells = <&speedbin_efuse>;
opp-shared;
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
opp-supported-hw = <0x77>;
clock-latency-ns = <200000>;
};
};
firmware {
scm {
compatible = "qcom,scm-msm8996";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0x0 0x80000000 0x0 0x0>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
mba_region: mba@91500000 {
reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
slpi_region: slpi@90b00000 {
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
venus_region: venus@90400000 {
reg = <0x0 0x90400000 0x0 0x700000>;
no-map;
};
adsp_region: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
no-map;
};
mpss_region: mpss@88800000 {
reg = <0x0 0x88800000 0x0 0x6200000>;
no-map;
};
smem_mem: smem-mem@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
memory@85800000 {
reg = <0x0 0x85800000 0x0 0x800000>;
no-map;
};
memory@86200000 {
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
rmtfs@86700000 {
compatible = "qcom,rmtfs-mem";
size = <0x0 0x200000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
zap_shader_region: gpu@8f200000 {
compatible = "shared-dma-pool";
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-msm8996";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8996-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp1: opp1 {
opp-level = <1>;
};
rpmpd_opp2: opp2 {
opp-level = <2>;
};
rpmpd_opp3: opp3 {
opp-level = <3>;
};
rpmpd_opp4: opp4 {
opp-level = <4>;
};
rpmpd_opp5: opp5 {
opp-level = <5>;
};
rpmpd_opp6: opp6 {
opp-level = <6>;
};
};
};
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 26>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_slpi_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
pcie_phy: phy@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x00034000 0x488>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_PCIE_PHY_BCR>,
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
status = "disabled";
pciephy_0: lane@35000 {
reg = <0x00035000 0x130>,
<0x00035200 0x200>,
<0x00035400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
pciephy_1: lane@36000 {
reg = <0x00036000 0x130>,
<0x00036200 0x200>,
<0x00036400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe1";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "lane1";
};
pciephy_2: lane@37000 {
reg = <0x00037000 0x130>,
<0x00037200 0x200>,
<0x00037400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe2";
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "lane2";
};
};
rpm_msg_ram: memory@68000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x00068000 0x6000>;
};
qfprom@74000 {
compatible = "qcom,qfprom";
reg = <0x00074000 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx_trim@24e {
reg = <0x24e 0x2>;
bits = <5 4>;
};
qusb2s_hstx_trim: hstx_trim@24f {
reg = <0x24f 0x1>;
bits = <1 4>;
};
speedbin_efuse: speedbin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
};
rng: rng@83000 {
compatible = "qcom,prng-ee";
reg = <0x00083000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00300000 0x90000>;
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
clock-names = "cxo2";
};
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
#qcom,sensors = <13>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@4ad000 {
compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
reg = <0x004ad000 0x1000>, /* TM */
<0x004ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
reg = <0x00740000 0x40000>;
};
tcsr: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x007a0000 0x18000>;
};
mmcc: clock-controller@8c0000 {
compatible = "qcom,mmcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x008c0000 0x40000>;
assigned-clocks = <&mmcc MMPLL9_PLL>,
<&mmcc MMPLL1_PLL>,
<&mmcc MMPLL3_PLL>,
<&mmcc MMPLL4_PLL>,
<&mmcc MMPLL5_PLL>;
assigned-clock-rates = <624000000>,
<810000000>,
<980000000>,
<960000000>,
<825000000>;
};
mdss: mdss@900000 {
compatible = "qcom,mdss";
reg = <0x00900000 0x1000>,
<0x009b0000 0x1040>,
<0x009b8000 0x1040>;
reg-names = "mdss_phys",
"vbif_phys",
"vbif_nrt_phys";
power-domains = <&mmcc MDSS_GDSC>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&mmcc MDSS_AHB_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdp: mdp@901000 {
compatible = "qcom,mdp5";
reg = <0x00901000 0x90000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"iommu",
"vsync";
iommus = <&mdp_smmu 0>;
assigned-clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
assigned-clock-rates = <300000000>,
<19200000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp5_intf3_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
port@1 {
reg = <1>;
mdp5_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi0: dsi@994000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x00994000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>;
clock-names = "mdp_core",
"byte",
"iface",
"bus",
"core_mmss",
"pixel",
"core";
phys = <&dsi0_phy>;
phy-names = "dsi";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: dsi-phy@994400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00994400 0x100>,
<0x00994500 0x300>,
<0x00994800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
clock-names = "iface", "ref";
status = "disabled";
};
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
interrupt-parent = <&mdss>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_HDMI_CLK>,
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names =
"mdp_core",
"iface",
"core",
"alt_iface",
"extp";
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
#sound-dai-cells = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&mdp5_intf3_out>;
};
};
};
};
hdmi_phy: hdmi-phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
<0x009a0a00 0x124>,
<0x009a0c00 0x124>,
<0x009a0e00 0x124>,
<0x009a1000 0x124>,
<0x009a1200 0x0c8>;
reg-names = "hdmi_pll",
"hdmi_tx_l0",
"hdmi_tx_l1",
"hdmi_tx_l2",
"hdmi_tx_l3",
"hdmi_phy";
clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>;
clock-names = "iface",
"ref";
status = "disabled";
};
};
gpu: gpu@b00000 {
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0x00b00000 0x3f000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
<&mmcc GPU_AHB_CLK>,
<&mmcc GPU_GX_RBBMTIMER_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_MMSS_BIMC_GFX_CLK>;
clock-names = "core",
"iface",
"rbbmtimer",
"mem",
"mem_iface";
power-domains = <&mmcc GPU_GX_GDSC>;
iommus = <&adreno_smmu 0>;
nvmem-cells = <&speedbin_efuse>;
nvmem-cell-names = "speed_bin";
qcom,gpu-quirk-two-pass-use-wfi;
qcom,gpu-quirk-fault-detect-mask;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
#cooling-cells = <2>;
gpu_opp_table: opp-table {
compatible ="operating-points-v2";
/*
* 624Mhz and 560Mhz are only available on speed
* bin (1 << 0). All the rest are available on
* all bins of the hardware
*/
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
opp-supported-hw = <0x01>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-supported-hw = <0x01>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
opp-supported-hw = <0xFF>;
};
opp-401800000 {
opp-hz = /bits/ 64 <401800000>;
opp-supported-hw = <0xFF>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-supported-hw = <0xFF>;
};
opp-214000000 {
opp-hz = /bits/ 64 <214000000>;
opp-supported-hw = <0xFF>;
};
opp-133000000 {
opp-hz = /bits/ 64 <133000000>;
opp-supported-hw = <0xFF>;
};
};
zap-shader {
memory-region = <&zap_shader_region>;
};
};
tlmm: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 150>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1_spi1_default: blsp1-spi1-default {
spi {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
cs {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
};
};
blsp1_spi1_sleep: blsp1-spi1-sleep {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
blsp2_uart2_2pins_default: blsp2-uart1-2pins {
pins = "gpio4", "gpio5";
function = "blsp_uart8";
drive-strength = <16>;
bias-disable;
};
blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c2_default: blsp2-i2c2 {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <16>;
bias-disable;
};
blsp2_i2c2_sleep: blsp2-i2c2-sleep {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
cci0_default: cci0-default {
pins = "gpio17", "gpio18";
function = "cci_i2c";
drive-strength = <16>;
bias-disable;
};
camera0_state_on:
camera_rear_default: camera-rear-default {
camera0_mclk: mclk0 {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
camera0_rst: rst {
pins = "gpio25";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
camera0_pwdn: pwdn {
pins = "gpio26";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
cci1_default: cci1-default {
pins = "gpio19", "gpio20";
function = "cci_i2c";
drive-strength = <16>;
bias-disable;
};
camera1_state_on:
camera_board_default: camera-board-default {
mclk1 {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
pwdn {
pins = "gpio98";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
rst {
pins = "gpio104";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
camera2_state_on:
camera_front_default: camera-front-default {
camera2_mclk: mclk2 {
pins = "gpio15";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
camera2_rst: rst {
pins = "gpio23";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pwdn {
pins = "gpio133";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
pcie0_state_on: pcie0-state-on {
perst {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
wake {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_state_off: pcie0-state-off {
perst {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
pins = "gpio36";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
blsp1_i2c3_default: blsp1-i2c2-default {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <16>;
bias-disable = <0>;
};
blsp1_i2c3_sleep: blsp1-i2c2-sleep {
pins = "gpio47", "gpio48";
function = "gpio";
drive-strength = <2>;
bias-disable = <0>;
};
blsp2_uart3_4pins_default: blsp2-uart2-4pins {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <16>;
bias-disable;
};
blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <2>;
bias-disable;
};
wcd_intr_default: wcd-intr-default{
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
blsp2_i2c1_default: blsp2-i2c1 {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <16>;
bias-disable;
};
blsp2_i2c1_sleep: blsp2-i2c0-sleep {
pins = "gpio55", "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c5_default: blsp2-i2c5 {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
/* Sleep state for BLSP2_I2C5 is missing.. */
cdc_reset_active: cdc-reset-active {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
bias-pull-down;
output-high;
};
cdc_reset_sleep: cdc-reset-sleep {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
blsp2_spi6_default: blsp2-spi5-default {
spi {
pins = "gpio85", "gpio86", "gpio88";
function = "blsp_spi12";
drive-strength = <12>;
bias-disable;
};
cs {
pins = "gpio87";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-high;
};
};
blsp2_spi6_sleep: blsp2-spi5-sleep {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
blsp2_i2c6_default: blsp2-i2c6 {
pins = "gpio87", "gpio88";
function = "blsp_i2c12";
drive-strength = <16>;
bias-disable;
};
blsp2_i2c6_sleep: blsp2-i2c6-sleep {
pins = "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
pcie1_state_on: pcie1-state-on {
perst {
pins = "gpio130";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
pins = "gpio131";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
wake {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
pcie1_state_off: pcie1-state-off {
/* Perst is missing? */
clkreq {
pins = "gpio131";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
pcie2_state_on: pcie2-state-on {
perst {
pins = "gpio114";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
pins = "gpio115";
function = "pci_e2";
drive-strength = <2>;
bias-pull-up;
};
wake {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
pcie2_state_off: pcie2-state-off {
/* Perst is missing? */
clkreq {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wake {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
sdc1_state_on: sdc1-state-on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_state_off: sdc1-state-off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc2_state_on: sdc2-clk-on {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_state_off: sdc2-clk-off {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
};
};
spmi_bus: qcom,spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
<0x04c00000 0x800000>,
<0x05800000 0x200000>,
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
agnoc@0 {
power-domains = <&gcc AGGRE0_NOC_GDSC>;
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pcie0: pcie@600000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
reg = <0x00600000 0x2000>,
<0x0c000000 0xf1d>,
<0x0c000f20 0xa8>,
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
phys = <&pciephy_0>;
phy-names = "pciephy";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
device_type = "pci";
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_state_on>;
pinctrl-1 = <&pcie0_state_off>;
linux,pci-domain = <0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
pcie1: pcie@608000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
status = "disabled";
reg = <0x00608000 0x2000>,
<0x0d000000 0xf1d>,
<0x0d000f20 0xa8>,
<0x0d100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
phys = <&pciephy_1>;
phy-names = "pciephy";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
device_type = "pci";
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_state_on>;
pinctrl-1 = <&pcie1_state_off>;
linux,pci-domain = <1>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
pcie2: pcie@610000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
status = "disabled";
reg = <0x00610000 0x2000>,
<0x0e000000 0xf1d>,
<0x0e000f20 0xa8>,
<0x0e100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
phys = <&pciephy_2>;
phy-names = "pciephy";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
device_type = "pci";
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_state_on>;
pinctrl-1 = <&pcie2_state_off>;
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
};
ufshc: ufshc@624000 {
compatible = "qcom,ufshc";
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_lane>;
phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>;
clock-names =
"core_clk_src",
"core_clk",
"bus_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro_src",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks =
<&gcc UFS_AXI_CLK_SRC>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_UFS_AHB_CLK>,
<&gcc UFS_ICE_CORE_CLK_SRC>,
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_ICE_CORE_CLK>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
freq-table-hz =
<100000000 200000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>,
<150000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
lanes-per-direction = <1>;
#reset-cells = <1>;
status = "disabled";
ufs_variant {
compatible = "qcom,ufs_variant";
};
};
ufsphy: phy@627000 {
compatible = "qcom,msm8996-qmp-ufs-phy";
reg = <0x00627000 0x1c4>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
status = "disabled";
ufsphy_lane: lanes@627400 {
reg = <0x627400 0x12c>,
<0x627600 0x200>,
<0x627c00 0x1b4>;
#phy-cells = <0>;
};
};
camss: camss@a00000 {
compatible = "qcom,msm8996-camss";
reg = <0x00a34000 0x1000>,
<0x00a00030 0x4>,
<0x00a35000 0x1000>,
<0x00a00038 0x4>,
<0x00a36000 0x1000>,
<0x00a00040 0x4>,
<0x00a30000 0x100>,
<0x00a30400 0x100>,
<0x00a30800 0x100>,
<0x00a30c00 0x100>,
<0x00a31000 0x500>,
<0x00a00020 0x10>,
<0x00a10000 0x1000>,
<0x00a14000 0x1000>;
reg-names = "csiphy0",
"csiphy0_clk_mux",
"csiphy1",
"csiphy1_clk_mux",
"csiphy2",
"csiphy2_clk_mux",
"csid0",
"csid1",
"csid2",
"csid3",
"ispif",
"csi_clk_mux",
"vfe0",
"vfe1";
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",
"csid0",
"csid1",
"csid2",
"csid3",
"ispif",
"vfe0",
"vfe1";
power-domains = <&mmcc VFE0_GDSC>,
<&mmcc VFE1_GDSC>;
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_ISPIF_AHB_CLK>,
<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
<&mmcc CAMSS_CSI0_AHB_CLK>,
<&mmcc CAMSS_CSI0_CLK>,
<&mmcc CAMSS_CSI0PHY_CLK>,
<&mmcc CAMSS_CSI0PIX_CLK>,
<&mmcc CAMSS_CSI0RDI_CLK>,
<&mmcc CAMSS_CSI1_AHB_CLK>,
<&mmcc CAMSS_CSI1_CLK>,
<&mmcc CAMSS_CSI1PHY_CLK>,
<&mmcc CAMSS_CSI1PIX_CLK>,
<&mmcc CAMSS_CSI1RDI_CLK>,
<&mmcc CAMSS_CSI2_AHB_CLK>,
<&mmcc CAMSS_CSI2_CLK>,
<&mmcc CAMSS_CSI2PHY_CLK>,
<&mmcc CAMSS_CSI2PIX_CLK>,
<&mmcc CAMSS_CSI2RDI_CLK>,
<&mmcc CAMSS_CSI3_AHB_CLK>,
<&mmcc CAMSS_CSI3_CLK>,
<&mmcc CAMSS_CSI3PHY_CLK>,
<&mmcc CAMSS_CSI3PIX_CLK>,
<&mmcc CAMSS_CSI3RDI_CLK>,
<&mmcc CAMSS_AHB_CLK>,
<&mmcc CAMSS_VFE0_CLK>,
<&mmcc CAMSS_CSI_VFE0_CLK>,
<&mmcc CAMSS_VFE0_AHB_CLK>,
<&mmcc CAMSS_VFE0_STREAM_CLK>,
<&mmcc CAMSS_VFE1_CLK>,
<&mmcc CAMSS_CSI_VFE1_CLK>,
<&mmcc CAMSS_VFE1_AHB_CLK>,
<&mmcc CAMSS_VFE1_STREAM_CLK>,
<&mmcc CAMSS_VFE_AHB_CLK>,
<&mmcc CAMSS_VFE_AXI_CLK>;
clock-names = "top_ahb",
"ispif_ahb",
"csiphy0_timer",
"csiphy1_timer",
"csiphy2_timer",
"csi0_ahb",
"csi0",
"csi0_phy",
"csi0_pix",
"csi0_rdi",
"csi1_ahb",
"csi1",
"csi1_phy",
"csi1_pix",
"csi1_rdi",
"csi2_ahb",
"csi2",
"csi2_phy",
"csi2_pix",
"csi2_rdi",
"csi3_ahb",
"csi3",
"csi3_phy",
"csi3_pix",
"csi3_rdi",
"ahb",
"vfe0",
"csi_vfe0",
"vfe0_ahb",
"vfe0_stream",
"vfe1",
"csi_vfe1",
"vfe1_ahb",
"vfe1_stream",
"vfe_ahb",
"vfe_axi";
iommus = <&vfe_smmu 0>,
<&vfe_smmu 1>,
<&vfe_smmu 2>,
<&vfe_smmu 3>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
cci: cci@a0c000 {
compatible = "qcom,msm8996-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0c000 0x1000>;
interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
power-domains = <&mmcc CAMSS_GDSC>;
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
<&mmcc CAMSS_CCI_AHB_CLK>,
<&mmcc CAMSS_CCI_CLK>,
<&mmcc CAMSS_AHB_CLK>;
clock-names = "camss_top_ahb",
"cci_ahb",
"cci",
"camss_ahb";
assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
<&mmcc CAMSS_CCI_CLK>;
assigned-clock-rates = <80000000>, <37500000>;
pinctrl-names = "default";
pinctrl-0 = <&cci0_default &cci1_default>;
status = "disabled";
cci_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
adreno_smmu: iommu@b40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
clocks = <&mmcc GPU_AHB_CLK>,
<&gcc GCC_MMSS_BIMC_GFX_CLK>;
clock-names = "iface", "bus";
power-domains = <&mmcc GPU_GDSC>;
};
venus: video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc VENUS_GDSC>;
clocks = <&mmcc VIDEO_CORE_CLK>,
<&mmcc VIDEO_AHB_CLK>,
<&mmcc VIDEO_AXI_CLK>,
<&mmcc VIDEO_MAXI_CLK>;
clock-names = "core", "iface", "bus", "mbus";
iommus = <&venus_smmu 0x00>,
<&venus_smmu 0x01>,
<&venus_smmu 0x0a>,
<&venus_smmu 0x07>,
<&venus_smmu 0x0e>,
<&venus_smmu 0x0f>,
<&venus_smmu 0x08>,
<&venus_smmu 0x09>,
<&venus_smmu 0x0b>,
<&venus_smmu 0x0c>,
<&venus_smmu 0x0d>,
<&venus_smmu 0x10>,
<&venus_smmu 0x11>,
<&venus_smmu 0x21>,
<&venus_smmu 0x28>,
<&venus_smmu 0x29>,
<&venus_smmu 0x2b>,
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
status = "disabled";
video-decoder {
compatible = "venus-decoder";
clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE0_GDSC>;
};
video-encoder {
compatible = "venus-encoder";
clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE1_GDSC>;
};
};
mdp_smmu: iommu@d00000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x00d00000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
clocks = <&mmcc SMMU_MDP_AHB_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>;
clock-names = "iface", "bus";
power-domains = <&mmcc MDSS_GDSC>;
};
venus_smmu: iommu@d40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x00d40000 0x20000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
<&mmcc SMMU_VIDEO_AXI_CLK>;
clock-names = "iface", "bus";
#iommu-cells = <1>;
status = "okay";
};
vfe_smmu: iommu@da0000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x00da0000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
clocks = <&mmcc SMMU_VFE_AHB_CLK>,
<&mmcc SMMU_VFE_AXI_CLK>;
clock-names = "iface",
"bus";
#iommu-cells = <1>;
};
lpass_q6_smmu: iommu@1600000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x01600000 0x20000>;
#iommu-cells = <1>;
power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
<&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
clock-names = "iface", "bus";
};
stm@3002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x3002000 0x1000>,
<0x8280000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint =
<&funnel0_in>;
};
};
};
};
tpiu@3020000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0x3020000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
tpiu_in: endpoint {
remote-endpoint =
<&replicator_out1>;
};
};
};
};
funnel@3021000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3021000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel0_in: endpoint {
remote-endpoint =
<&stm_out>;
};
};
};
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint =
<&merge_funnel_in0>;
};
};
};
};
funnel@3022000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3022000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel1_in: endpoint {
remote-endpoint =
<&apss_merge_funnel_out>;
};
};
};
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint =
<&merge_funnel_in1>;
};
};
};
};
funnel@3023000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3023000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
funnel2_out: endpoint {
remote-endpoint =
<&merge_funnel_in2>;
};
};
};
};
funnel@3025000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3025000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint =
<&funnel0_out>;
};
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint =
<&funnel1_out>;
};
};
port@2 {
reg = <2>;
merge_funnel_in2: endpoint {
remote-endpoint =
<&funnel2_out>;
};
};
};
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
};
};
replicator@3026000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x3026000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
replicator_in: endpoint {
remote-endpoint =
<&etf_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
<&etr_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
<&tpiu_in>;
};
};
};
};
etf@3027000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3027000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
};
};
};
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
};
etr@3028000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3028000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
arm,scatter-gather;
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out0>;
};
};
};
};
debug@3810000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3810000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
};
etm@3840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3840000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&apss_funnel0_in0>;
};
};
};
};
debug@3910000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3910000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
};
etm@3940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3940000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&apss_funnel0_in1>;
};
};
};
};
funnel@39b0000 { /* APSS Funnel 0 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x39b0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel0_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel0_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
};
out-ports {
port {
apss_funnel0_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in0>;
};
};
};
};
debug@3a10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3a10000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
};
etm@3a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3a40000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU2>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&apss_funnel1_in0>;
};
};
};
};
debug@3b10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3b10000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
};
etm@3b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3b40000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU3>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&apss_funnel1_in1>;
};
};
};
};
funnel@3bb0000 { /* APSS Funnel 1 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bb0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel1_in0: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@1 {
reg = <1>;
apss_funnel1_in1: endpoint {
remote-endpoint = <&etm3_out>;
};
};
};
out-ports {
port {
apss_funnel1_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in1>;
};
};
};
};
funnel@3bc0000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bc0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_merge_funnel_in0: endpoint {
remote-endpoint =
<&apss_funnel0_out>;
};
};
port@1 {
reg = <1>;
apss_merge_funnel_in1: endpoint {
remote-endpoint =
<&apss_funnel1_out>;
};
};
};
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint =
<&funnel1_in>;
};
};
};
};
kryocc: clock-controller@6400000 {
compatible = "qcom,msm8996-apcc";
reg = <0x06400000 0x90000>;
clock-names = "xo";
clocks = <&xo_board>;
#clock-cells = <1>;
};
usb3: usb@6af8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
reg = <0x06af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
usb3_dwc3: dwc3@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
};
};
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x07410000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
status = "disabled";
ssusb_phy_0: lane@7410200 {
reg = <0x07410200 0x200>,
<0x07410400 0x130>,
<0x07410600 0x1a8>;
#phy-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
};
};
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x07411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
status = "disabled";
};
hsusb_phy2: phy@7412000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x07412000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX2_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
nvmem-cells = <&qusb2s_hstx_trim>;
status = "disabled";
};
sdhc1: sdhci@7464900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x07464900 0x11c>, <0x07464000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
bus-width = <8>;
non-removable;
status = "disabled";
};
sdhc2: sdhci@74a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_state_on>;
pinctrl-1 = <&sdc2_state_off>;
bus-width = <4>;
status = "disabled";
};
blsp1_dma: dma@7544000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07544000 0x2b000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
qcom,controlled-remotely;
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart2: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_spi1: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi1_default>;
pinctrl-1 = <&blsp1_spi1_sleep>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>;
dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_dma: dma@7584000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07584000 0x2b000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
qcom,controlled-remotely;
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp2_uart3: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c5: i2c@75b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c5_default>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-