blob: ad6532443a785b1305a752c58ce7ed5bdb565b02 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0
/*
* R8A779A0 processor support - PFC hardware block.
*
* Copyright (C) 2020 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*/
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
*/
/* GPSR0 */
#define GPSR0_27 FM(MMC_D7)
#define GPSR0_26 FM(MMC_D6)
#define GPSR0_25 FM(MMC_D5)
#define GPSR0_24 FM(MMC_D4)
#define GPSR0_23 FM(MMC_SD_CLK)
#define GPSR0_22 FM(MMC_SD_D3)
#define GPSR0_21 FM(MMC_SD_D2)
#define GPSR0_20 FM(MMC_SD_D1)
#define GPSR0_19 FM(MMC_SD_D0)
#define GPSR0_18 FM(MMC_SD_CMD)
#define GPSR0_17 FM(MMC_DS)
#define GPSR0_16 FM(SD_CD)
#define GPSR0_15 FM(SD_WP)
#define GPSR0_14 FM(RPC_INT_N)
#define GPSR0_13 FM(RPC_WP_N)
#define GPSR0_12 FM(RPC_RESET_N)
#define GPSR0_11 FM(QSPI1_SSL)
#define GPSR0_10 FM(QSPI1_IO3)
#define GPSR0_9 FM(QSPI1_IO2)
#define GPSR0_8 FM(QSPI1_MISO_IO1)
#define GPSR0_7 FM(QSPI1_MOSI_IO0)
#define GPSR0_6 FM(QSPI1_SPCLK)
#define GPSR0_5 FM(QSPI0_SSL)
#define GPSR0_4 FM(QSPI0_IO3)
#define GPSR0_3 FM(QSPI0_IO2)
#define GPSR0_2 FM(QSPI0_MISO_IO1)
#define GPSR0_1 FM(QSPI0_MOSI_IO0)
#define GPSR0_0 FM(QSPI0_SPCLK)
/* GPSR1 */
#define GPSR1_30 F_(GP1_30, IP3SR1_27_24)
#define GPSR1_29 F_(GP1_29, IP3SR1_23_20)
#define GPSR1_28 F_(GP1_28, IP3SR1_19_16)
#define GPSR1_27 F_(IRQ3, IP3SR1_15_12)
#define GPSR1_26 F_(IRQ2, IP3SR1_11_8)
#define GPSR1_25 F_(IRQ1, IP3SR1_7_4)
#define GPSR1_24 F_(IRQ0, IP3SR1_3_0)
#define GPSR1_23 F_(MSIOF2_SS2, IP2SR1_31_28)
#define GPSR1_22 F_(MSIOF2_SS1, IP2SR1_27_24)
#define GPSR1_21 F_(MSIOF2_SYNC, IP2SR1_23_20)
#define GPSR1_20 F_(MSIOF2_SCK, IP2SR1_19_16)
#define GPSR1_19 F_(MSIOF2_TXD, IP2SR1_15_12)
#define GPSR1_18 F_(MSIOF2_RXD, IP2SR1_11_8)
#define GPSR1_17 F_(MSIOF1_SS2, IP2SR1_7_4)
#define GPSR1_16 F_(MSIOF1_SS1, IP2SR1_3_0)
#define GPSR1_15 F_(MSIOF1_SYNC, IP1SR1_31_28)
#define GPSR1_14 F_(MSIOF1_SCK, IP1SR1_27_24)
#define GPSR1_13 F_(MSIOF1_TXD, IP1SR1_23_20)
#define GPSR1_12 F_(MSIOF1_RXD, IP1SR1_19_16)
#define GPSR1_11 F_(MSIOF0_SS2, IP1SR1_15_12)
#define GPSR1_10 F_(MSIOF0_SS1, IP1SR1_11_8)
#define GPSR1_9 F_(MSIOF0_SYNC, IP1SR1_7_4)
#define GPSR1_8 F_(MSIOF0_SCK, IP1SR1_3_0)
#define GPSR1_7 F_(MSIOF0_TXD, IP0SR1_31_28)
#define GPSR1_6 F_(MSIOF0_RXD, IP0SR1_27_24)
#define GPSR1_5 F_(HTX0, IP0SR1_23_20)
#define GPSR1_4 F_(HCTS0_N, IP0SR1_19_16)
#define GPSR1_3 F_(HRTS0_N, IP0SR1_15_12)
#define GPSR1_2 F_(HSCK0, IP0SR1_11_8)
#define GPSR1_1 F_(HRX0, IP0SR1_7_4)
#define GPSR1_0 F_(SCIF_CLK, IP0SR1_3_0)
/* GPSR2 */
#define GPSR2_24 FM(TCLK2_A)
#define GPSR2_23 F_(TCLK1_A, IP2SR2_31_28)
#define GPSR2_22 F_(TPU0TO1, IP2SR2_27_24)
#define GPSR2_21 F_(TPU0TO0, IP2SR2_23_20)
#define GPSR2_20 F_(CLK_EXTFXR, IP2SR2_19_16)
#define GPSR2_19 F_(RXDB_EXTFXR, IP2SR2_15_12)
#define GPSR2_18 F_(FXR_TXDB, IP2SR2_11_8)
#define GPSR2_17 F_(RXDA_EXTFXR_A, IP2SR2_7_4)
#define GPSR2_16 F_(FXR_TXDA_A, IP2SR2_3_0)
#define GPSR2_15 F_(GP2_15, IP1SR2_31_28)
#define GPSR2_14 F_(GP2_14, IP1SR2_27_24)
#define GPSR2_13 F_(GP2_13, IP1SR2_23_20)
#define GPSR2_12 F_(GP2_12, IP1SR2_19_16)
#define GPSR2_11 F_(GP2_11, IP1SR2_15_12)
#define GPSR2_10 F_(GP2_10, IP1SR2_11_8)
#define GPSR2_9 F_(GP2_09, IP1SR2_7_4)
#define GPSR2_8 F_(GP2_08, IP1SR2_3_0)
#define GPSR2_7 F_(GP2_07, IP0SR2_31_28)
#define GPSR2_6 F_(GP2_06, IP0SR2_27_24)
#define GPSR2_5 F_(GP2_05, IP0SR2_23_20)
#define GPSR2_4 F_(GP2_04, IP0SR2_19_16)
#define GPSR2_3 F_(GP2_03, IP0SR2_15_12)
#define GPSR2_2 F_(GP2_02, IP0SR2_11_8)
#define GPSR2_1 F_(IPC_CLKOUT, IP0SR2_7_4)
#define GPSR2_0 F_(IPC_CLKIN, IP0SR2_3_0)
/* GPSR3 */
#define GPSR3_16 FM(CANFD7_RX)
#define GPSR3_15 FM(CANFD7_TX)
#define GPSR3_14 FM(CANFD6_RX)
#define GPSR3_13 F_(CANFD6_TX, IP1SR3_23_20)
#define GPSR3_12 F_(CANFD5_RX, IP1SR3_19_16)
#define GPSR3_11 F_(CANFD5_TX, IP1SR3_15_12)
#define GPSR3_10 F_(CANFD4_RX, IP1SR3_11_8)
#define GPSR3_9 F_(CANFD4_TX, IP1SR3_7_4)
#define GPSR3_8 F_(CANFD3_RX, IP1SR3_3_0)
#define GPSR3_7 F_(CANFD3_TX, IP0SR3_31_28)
#define GPSR3_6 F_(CANFD2_RX, IP0SR3_27_24)
#define GPSR3_5 F_(CANFD2_TX, IP0SR3_23_20)
#define GPSR3_4 FM(CANFD1_RX)
#define GPSR3_3 FM(CANFD1_TX)
#define GPSR3_2 F_(CANFD0_RX, IP0SR3_11_8)
#define GPSR3_1 F_(CANFD0_TX, IP0SR3_7_4)
#define GPSR3_0 FM(CAN_CLK)
/* GPSR4 */
#define GPSR4_26 FM(AVS1)
#define GPSR4_25 FM(AVS0)
#define GPSR4_24 FM(PCIE3_CLKREQ_N)
#define GPSR4_23 FM(PCIE2_CLKREQ_N)
#define GPSR4_22 FM(PCIE1_CLKREQ_N)
#define GPSR4_21 FM(PCIE0_CLKREQ_N)
#define GPSR4_20 F_(AVB0_AVTP_PPS, IP2SR4_19_16)
#define GPSR4_19 F_(AVB0_AVTP_CAPTURE, IP2SR4_15_12)
#define GPSR4_18 F_(AVB0_AVTP_MATCH, IP2SR4_11_8)
#define GPSR4_17 F_(AVB0_LINK, IP2SR4_7_4)
#define GPSR4_16 FM(AVB0_PHY_INT)
#define GPSR4_15 F_(AVB0_MAGIC, IP1SR4_31_28)
#define GPSR4_14 F_(AVB0_MDC, IP1SR4_27_24)
#define GPSR4_13 F_(AVB0_MDIO, IP1SR4_23_20)
#define GPSR4_12 F_(AVB0_TXCREFCLK, IP1SR4_19_16)
#define GPSR4_11 F_(AVB0_TD3, IP1SR4_15_12)
#define GPSR4_10 F_(AVB0_TD2, IP1SR4_11_8)
#define GPSR4_9 F_(AVB0_TD1, IP1SR4_7_4)
#define GPSR4_8 F_(AVB0_TD0, IP1SR4_3_0)
#define GPSR4_7 F_(AVB0_TXC, IP0SR4_31_28)
#define GPSR4_6 F_(AVB0_TX_CTL, IP0SR4_27_24)
#define GPSR4_5 F_(AVB0_RD3, IP0SR4_23_20)
#define GPSR4_4 F_(AVB0_RD2, IP0SR4_19_16)
#define GPSR4_3 F_(AVB0_RD1, IP0SR4_15_12)
#define GPSR4_2 F_(AVB0_RD0, IP0SR4_11_8)
#define GPSR4_1 F_(AVB0_RXC, IP0SR4_7_4)
#define GPSR4_0 F_(AVB0_RX_CTL, IP0SR4_3_0)
/* GPSR5 */
#define GPSR5_20 F_(AVB1_AVTP_PPS, IP2SR5_19_16)
#define GPSR5_19 F_(AVB1_AVTP_CAPTURE, IP2SR5_15_12)
#define GPSR5_18 F_(AVB1_AVTP_MATCH, IP2SR5_11_8)
#define GPSR5_17 F_(AVB1_LINK, IP2SR5_7_4)
#define GPSR5_16 FM(AVB1_PHY_INT)
#define GPSR5_15 F_(AVB1_MAGIC, IP1SR5_31_28)
#define GPSR5_14 F_(AVB1_MDC, IP1SR5_27_24)
#define GPSR5_13 F_(AVB1_MDIO, IP1SR5_23_20)
#define GPSR5_12 F_(AVB1_TXCREFCLK, IP1SR5_19_16)
#define GPSR5_11 F_(AVB1_TD3, IP1SR5_15_12)
#define GPSR5_10 F_(AVB1_TD2, IP1SR5_11_8)
#define GPSR5_9 F_(AVB1_TD1, IP1SR5_7_4)
#define GPSR5_8 F_(AVB1_TD0, IP1SR5_3_0)
#define GPSR5_7 F_(AVB1_TXC, IP0SR5_31_28)
#define GPSR5_6 F_(AVB1_TX_CTL, IP0SR5_27_24)
#define GPSR5_5 F_(AVB1_RD3, IP0SR5_23_20)
#define GPSR5_4 F_(AVB1_RD2, IP0SR5_19_16)
#define GPSR5_3 F_(AVB1_RD1, IP0SR5_15_12)
#define GPSR5_2 F_(AVB1_RD0, IP0SR5_11_8)
#define GPSR5_1 F_(AVB1_RXC, IP0SR5_7_4)
#define GPSR5_0 F_(AVB1_RX_CTL, IP0SR5_3_0)
/* GPSR6 */
#define GPSR6_20 FM(AVB2_AVTP_PPS)
#define GPSR6_19 FM(AVB2_AVTP_CAPTURE)
#define GPSR6_18 FM(AVB2_AVTP_MATCH)
#define GPSR6_17 FM(AVB2_LINK)
#define GPSR6_16 FM(AVB2_PHY_INT)
#define GPSR6_15 FM(AVB2_MAGIC)
#define GPSR6_14 FM(AVB2_MDC)
#define GPSR6_13 FM(AVB2_MDIO)
#define GPSR6_12 FM(AVB2_TXCREFCLK)
#define GPSR6_11 FM(AVB2_TD3)
#define GPSR6_10 FM(AVB2_TD2)
#define GPSR6_9 FM(AVB2_TD1)
#define GPSR6_8 FM(AVB2_TD0)
#define GPSR6_7 FM(AVB2_TXC)
#define GPSR6_6 FM(AVB2_TX_CTL)
#define GPSR6_5 FM(AVB2_RD3)
#define GPSR6_4 FM(AVB2_RD2)
#define GPSR6_3 FM(AVB2_RD1)
#define GPSR6_2 FM(AVB2_RD0)
#define GPSR6_1 FM(AVB2_RXC)
#define GPSR6_0 FM(AVB2_RX_CTL)
/* GPSR7 */
#define GPSR7_20 FM(AVB3_AVTP_PPS)
#define GPSR7_19 FM(AVB3_AVTP_CAPTURE)
#define GPSR7_18 FM(AVB3_AVTP_MATCH)
#define GPSR7_17 FM(AVB3_LINK)
#define GPSR7_16 FM(AVB3_PHY_INT)
#define GPSR7_15 FM(AVB3_MAGIC)
#define GPSR7_14 FM(AVB3_MDC)
#define GPSR7_13 FM(AVB3_MDIO)
#define GPSR7_12 FM(AVB3_TXCREFCLK)
#define GPSR7_11 FM(AVB3_TD3)
#define GPSR7_10 FM(AVB3_TD2)
#define GPSR7_9 FM(AVB3_TD1)
#define GPSR7_8 FM(AVB3_TD0)
#define GPSR7_7 FM(AVB3_TXC)
#define GPSR7_6 FM(AVB3_TX_CTL)
#define GPSR7_5 FM(AVB3_RD3)
#define GPSR7_4 FM(AVB3_RD2)
#define GPSR7_3 FM(AVB3_RD1)
#define GPSR7_2 FM(AVB3_RD0)
#define GPSR7_1 FM(AVB3_RXC)
#define GPSR7_0 FM(AVB3_RX_CTL)
/* GPSR8 */
#define GPSR8_20 FM(AVB4_AVTP_PPS)
#define GPSR8_19 FM(AVB4_AVTP_CAPTURE)
#define GPSR8_18 FM(AVB4_AVTP_MATCH)
#define GPSR8_17 FM(AVB4_LINK)
#define GPSR8_16 FM(AVB4_PHY_INT)
#define GPSR8_15 FM(AVB4_MAGIC)
#define GPSR8_14 FM(AVB4_MDC)
#define GPSR8_13 FM(AVB4_MDIO)
#define GPSR8_12 FM(AVB4_TXCREFCLK)
#define GPSR8_11 FM(AVB4_TD3)
#define GPSR8_10 FM(AVB4_TD2)
#define GPSR8_9 FM(AVB4_TD1)
#define GPSR8_8 FM(AVB4_TD0)
#define GPSR8_7 FM(AVB4_TXC)
#define GPSR8_6 FM(AVB4_TX_CTL)
#define GPSR8_5 FM(AVB4_RD3)
#define GPSR8_4 FM(AVB4_RD2)
#define GPSR8_3 FM(AVB4_RD1)
#define GPSR8_2 FM(AVB4_RD0)
#define GPSR8_1 FM(AVB4_RXC)
#define GPSR8_0 FM(AVB4_RX_CTL)
/* GPSR9 */
#define GPSR9_20 FM(AVB5_AVTP_PPS)
#define GPSR9_19 FM(AVB5_AVTP_CAPTURE)
#define GPSR9_18 FM(AVB5_AVTP_MATCH)
#define GPSR9_17 FM(AVB5_LINK)
#define GPSR9_16 FM(AVB5_PHY_INT)
#define GPSR9_15 FM(AVB5_MAGIC)
#define GPSR9_14 FM(AVB5_MDC)
#define GPSR9_13 FM(AVB5_MDIO)
#define GPSR9_12 FM(AVB5_TXCREFCLK)
#define GPSR9_11 FM(AVB5_TD3)
#define GPSR9_10 FM(AVB5_TD2)
#define GPSR9_9 FM(AVB5_TD1)
#define GPSR9_8 FM(AVB5_TD0)
#define GPSR9_7 FM(AVB5_TXC)
#define GPSR9_6 FM(AVB5_TX_CTL)
#define GPSR9_5 FM(AVB5_RD3)
#define GPSR9_4 FM(AVB5_RD2)
#define GPSR9_3 FM(AVB5_RD1)
#define GPSR9_2 FM(AVB5_RD0)
#define GPSR9_1 FM(AVB5_RXC)
#define GPSR9_0 FM(AVB5_RX_CTL)
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR1_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_7_4 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_11_8 FM(HSCK0) FM(SCK0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_15_12 FM(HRTS0_N) FM(RTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_19_16 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_27_24 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_31_28 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR3) FM(A7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP1SR1_3_0 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR4) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_7_4 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_11_8 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR7) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DG2) FM(A12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_23_20 FM(MSIOF1_TXD) FM(HRX3) FM(SCK3) F_(0, 0) FM(DU_DG3) FM(A13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_27_24 FM(MSIOF1_SCK) FM(HSCK3) FM(CTS3_N) F_(0, 0) FM(DU_DG4) FM(A14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_31_28 FM(MSIOF1_SYNC) FM(HRTS3_N) FM(RTS3_N) F_(0, 0) FM(DU_DG5) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP2SR1_3_0 FM(MSIOF1_SS1) FM(HCTS3_N) FM(RX3) F_(0, 0) FM(DU_DG6) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_7_4 FM(MSIOF1_SS2) FM(HTX3) FM(TX3) F_(0, 0) FM(DU_DG7) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) FM(DU_DB2) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_15_12 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) FM(DU_DB3) FM(A19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_19_16 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) FM(DU_DB4) FM(A20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_23_20 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1_A) F_(0, 0) FM(DU_DB5) FM(A21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1_A) F_(0, 0) FM(DU_DB6) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_31_28 FM(MSIOF2_SS2) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(DU_DB7) FM(A23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP3SR1_3_0 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKOUT) FM(A24) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_7_4 FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_HSYNC) FM(A25) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_11_8 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_VSYNC) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_15_12 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_ODDF_DISP_CDE) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_7_4 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_11_8 FM(GP2_02) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_15_12 FM(GP2_03) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_19_16 FM(GP2_04) F_(0, 0) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) FM(D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_23_20 FM(GP2_05) FM(HSCK2) FM(MSIOF4_TXD) FM(SCK4) F_(0, 0) FM(D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_27_24 FM(GP2_06) FM(HCTS2_N) FM(MSIOF4_SCK) FM(CTS4_N) F_(0, 0) FM(D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_31_28 FM(GP2_07) FM(HRTS2_N) FM(MSIOF4_SYNC) FM(RTS4_N) F_(0, 0) FM(D8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP1SR2_3_0 FM(GP2_08) FM(HRX2) FM(MSIOF4_SS1) FM(RX4) F_(0, 0) FM(D9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_7_4 FM(GP2_09) FM(HTX2) FM(MSIOF4_SS2) FM(TX4) F_(0, 0) FM(D10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_11_8 FM(GP2_10) FM(TCLK2_B) FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) FM(D11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(GP2_11) FM(TCLK3) FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) FM(D12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_19_16 FM(GP2_12) FM(TCLK4) FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) FM(D13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_23_20 FM(GP2_13) F_(0, 0) FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_27_24 FM(GP2_14) FM(IRQ4) FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_31_28 FM(GP2_15) FM(IRQ5) FM(MSIOF5_SS2) FM(CPG_CPCKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP2SR2_3_0 FM(FXR_TXDA_A) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_7_4 FM(RXDA_EXTFXR_A) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) FM(BS_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_11_8 FM(FXR_TXDB) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_15_12 FM(RXDB_EXTFXR) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_19_16 FM(CLK_EXTFXR) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_23_20 FM(TPU0TO0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(RD_WR_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_27_24 FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP1SR3_3_0 FM(CANFD3_RX) F_(0, 0) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_7_4 FM(CANFD4_TX) F_(0, 0) FM(PWM4) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_11_8 FM(CANFD4_RX) F_(0, 0) F_(0, 0) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_7_4 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_15_12 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_23_20 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_27_24 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR4_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP1SR4_3_0 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_7_4 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_11_8 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_19_16 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_23_20 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_7_4 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_11_8 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_15_12 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_19_16 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_23_20 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_27_24 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR5_31_28 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP1SR5_3_0 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_7_4 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_11_8 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_15_12 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_23_20 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
GPSR1_30 \
GPSR1_29 \
GPSR1_28 \
GPSR0_27 GPSR1_27 \
GPSR0_26 GPSR1_26 GPSR4_26 \
GPSR0_25 GPSR1_25 GPSR4_25 \
GPSR0_24 GPSR1_24 GPSR2_24 GPSR4_24 \
GPSR0_23 GPSR1_23 GPSR2_23 GPSR4_23 \
GPSR0_22 GPSR1_22 GPSR2_22 GPSR4_22 \
GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 GPSR8_20 GPSR9_20 \
GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 GPSR8_19 GPSR9_19 \
GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 GPSR8_18 GPSR9_18 \
GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 GPSR8_17 GPSR9_17 \
GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 GPSR8_16 GPSR9_16 \
GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 GPSR8_15 GPSR9_15 \
GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 GPSR8_14 GPSR9_14 \
GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 GPSR9_13 \
GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 GPSR9_12 \
GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 GPSR9_11 \
GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 GPSR9_10 \
GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 GPSR9_9 \
GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 GPSR9_8 \
GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 GPSR9_7 \
GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 GPSR9_6 \
GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 GPSR9_5 \
GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 GPSR9_4 \
GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 GPSR9_3 \
GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 GPSR9_2 \
GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 GPSR9_1 \
GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0 GPSR9_0
#define PINMUX_IPSR \
\
FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
\
FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
\
FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \
FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \
FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \
FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \
FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \
FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \
FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \
FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \
\
FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \
FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
\
FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \
FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \
FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28
/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3)
#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3)
#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3)
#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3)
#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3)
#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3)
#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3)
#define PINMUX_MOD_SELS \
\
MOD_SEL2_14_15 \
MOD_SEL2_12_13 \
MOD_SEL2_10_11 \
MOD_SEL2_8_9 \
MOD_SEL2_6_7 \
MOD_SEL2_4_5 \
MOD_SEL2_2_3
#define PINMUX_PHYS \
FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
#define F_(x, y)
#define FM(x) FN_##x,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_FUNCTION_END,
#undef F_
#undef FM
#define F_(x, y)
#define FM(x) x##_MARK,
PINMUX_MARK_BEGIN,
PINMUX_GPSR
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_PHYS
PINMUX_MARK_END,
#undef F_
#undef FM
};
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
PINMUX_SINGLE(MMC_D7),
PINMUX_SINGLE(MMC_D6),
PINMUX_SINGLE(MMC_D5),
PINMUX_SINGLE(MMC_D4),
PINMUX_SINGLE(MMC_SD_CLK),
PINMUX_SINGLE(MMC_SD_D3),
PINMUX_SINGLE(MMC_SD_D2),
PINMUX_SINGLE(MMC_SD_D1),
PINMUX_SINGLE(MMC_SD_D0),
PINMUX_SINGLE(MMC_SD_CMD),
PINMUX_SINGLE(MMC_DS),
PINMUX_SINGLE(SD_CD),
PINMUX_SINGLE(SD_WP),
PINMUX_SINGLE(RPC_INT_N),
PINMUX_SINGLE(RPC_WP_N),
PINMUX_SINGLE(RPC_RESET_N),
PINMUX_SINGLE(QSPI1_SSL),
PINMUX_SINGLE(QSPI1_IO3),
PINMUX_SINGLE(QSPI1_IO2),
PINMUX_SINGLE(QSPI1_MISO_IO1),
PINMUX_SINGLE(QSPI1_MOSI_IO0),
PINMUX_SINGLE(QSPI1_SPCLK),
PINMUX_SINGLE(QSPI0_SSL),
PINMUX_SINGLE(QSPI0_IO3),
PINMUX_SINGLE(QSPI0_IO2),
PINMUX_SINGLE(QSPI0_MISO_IO1),
PINMUX_SINGLE(QSPI0_MOSI_IO0),
PINMUX_SINGLE(QSPI0_SPCLK),
PINMUX_SINGLE(TCLK2_A),
PINMUX_SINGLE(CANFD7_RX),
PINMUX_SINGLE(CANFD7_TX),
PINMUX_SINGLE(CANFD6_RX),
PINMUX_SINGLE(CANFD1_RX),
PINMUX_SINGLE(CANFD1_TX),
PINMUX_SINGLE(CAN_CLK),
PINMUX_SINGLE(AVS1),
PINMUX_SINGLE(AVS0),
PINMUX_SINGLE(PCIE3_CLKREQ_N),
PINMUX_SINGLE(PCIE2_CLKREQ_N),
PINMUX_SINGLE(PCIE1_CLKREQ_N),
PINMUX_SINGLE(PCIE0_CLKREQ_N),
PINMUX_SINGLE(AVB0_PHY_INT),
PINMUX_SINGLE(AVB0_MAGIC),
PINMUX_SINGLE(AVB0_MDC),
PINMUX_SINGLE(AVB0_MDIO),
PINMUX_SINGLE(AVB0_TXCREFCLK),
PINMUX_SINGLE(AVB1_PHY_INT),
PINMUX_SINGLE(AVB1_MAGIC),
PINMUX_SINGLE(AVB1_MDC),
PINMUX_SINGLE(AVB1_MDIO),
PINMUX_SINGLE(AVB1_TXCREFCLK),
PINMUX_SINGLE(AVB2_AVTP_PPS),
PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
PINMUX_SINGLE(AVB2_AVTP_MATCH),
PINMUX_SINGLE(AVB2_LINK),
PINMUX_SINGLE(AVB2_PHY_INT),
PINMUX_SINGLE(AVB2_MAGIC),
PINMUX_SINGLE(AVB2_MDC),
PINMUX_SINGLE(AVB2_MDIO),
PINMUX_SINGLE(AVB2_TXCREFCLK),
PINMUX_SINGLE(AVB2_TD3),
PINMUX_SINGLE(AVB2_TD2),
PINMUX_SINGLE(AVB2_TD1),
PINMUX_SINGLE(AVB2_TD0),
PINMUX_SINGLE(AVB2_TXC),
PINMUX_SINGLE(AVB2_TX_CTL),
PINMUX_SINGLE(AVB2_RD3),
PINMUX_SINGLE(AVB2_RD2),
PINMUX_SINGLE(AVB2_RD1),
PINMUX_SINGLE(AVB2_RD0),
PINMUX_SINGLE(AVB2_RXC),
PINMUX_SINGLE(AVB2_RX_CTL),
PINMUX_SINGLE(AVB3_AVTP_PPS),
PINMUX_SINGLE(AVB3_AVTP_CAPTURE),
PINMUX_SINGLE(AVB3_AVTP_MATCH),
PINMUX_SINGLE(AVB3_LINK),
PINMUX_SINGLE(AVB3_PHY_INT),
PINMUX_SINGLE(AVB3_MAGIC),
PINMUX_SINGLE(AVB3_MDC),
PINMUX_SINGLE(AVB3_MDIO),
PINMUX_SINGLE(AVB3_TXCREFCLK),
PINMUX_SINGLE(AVB3_TD3),
PINMUX_SINGLE(AVB3_TD2),
PINMUX_SINGLE(AVB3_TD1),
PINMUX_SINGLE(AVB3_TD0),
PINMUX_SINGLE(AVB3_TXC),
PINMUX_SINGLE(AVB3_TX_CTL),
PINMUX_SINGLE(AVB3_RD3),
PINMUX_SINGLE(AVB3_RD2),
PINMUX_SINGLE(AVB3_RD1),
PINMUX_SINGLE(AVB3_RD0),
PINMUX_SINGLE(AVB3_RXC),
PINMUX_SINGLE(AVB3_RX_CTL),
PINMUX_SINGLE(AVB4_AVTP_PPS),
PINMUX_SINGLE(AVB4_AVTP_CAPTURE),
PINMUX_SINGLE(AVB4_AVTP_MATCH),
PINMUX_SINGLE(AVB4_LINK),
PINMUX_SINGLE(AVB4_PHY_INT),
PINMUX_SINGLE(AVB4_MAGIC),
PINMUX_SINGLE(AVB4_MDC),
PINMUX_SINGLE(AVB4_MDIO),
PINMUX_SINGLE(AVB4_TXCREFCLK),
PINMUX_SINGLE(AVB4_TD3),
PINMUX_SINGLE(AVB4_TD2),
PINMUX_SINGLE(AVB4_TD1),
PINMUX_SINGLE(AVB4_TD0),
PINMUX_SINGLE(AVB4_TXC),
PINMUX_SINGLE(AVB4_TX_CTL),
PINMUX_SINGLE(AVB4_RD3),
PINMUX_SINGLE(AVB4_RD2),
PINMUX_SINGLE(AVB4_RD1),
PINMUX_SINGLE(AVB4_RD0),
PINMUX_SINGLE(AVB4_RXC),
PINMUX_SINGLE(AVB4_RX_CTL),
PINMUX_SINGLE(AVB5_AVTP_PPS),
PINMUX_SINGLE(AVB5_AVTP_CAPTURE),
PINMUX_SINGLE(AVB5_AVTP_MATCH),
PINMUX_SINGLE(AVB5_LINK),
PINMUX_SINGLE(AVB5_PHY_INT),
PINMUX_SINGLE(AVB5_MAGIC),
PINMUX_SINGLE(AVB5_MDC),
PINMUX_SINGLE(AVB5_MDIO),
PINMUX_SINGLE(AVB5_TXCREFCLK),
PINMUX_SINGLE(AVB5_TD3),
PINMUX_SINGLE(AVB5_TD2),
PINMUX_SINGLE(AVB5_TD1),
PINMUX_SINGLE(AVB5_TD0),
PINMUX_SINGLE(AVB5_TXC),
PINMUX_SINGLE(AVB5_TX_CTL),
PINMUX_SINGLE(AVB5_RD3),
PINMUX_SINGLE(AVB5_RD2),
PINMUX_SINGLE(AVB5_RD1),
PINMUX_SINGLE(AVB5_RD0),
PINMUX_SINGLE(AVB5_RXC),
PINMUX_SINGLE(AVB5_RX_CTL),
/* IP0SR1 */
PINMUX_IPSR_GPSR(IP0SR1_3_0, SCIF_CLK),
PINMUX_IPSR_GPSR(IP0SR1_3_0, A0),
PINMUX_IPSR_GPSR(IP0SR1_7_4, HRX0),
PINMUX_IPSR_GPSR(IP0SR1_7_4, RX0),
PINMUX_IPSR_GPSR(IP0SR1_7_4, A1),
PINMUX_IPSR_GPSR(IP0SR1_11_8, HSCK0),
PINMUX_IPSR_GPSR(IP0SR1_11_8, SCK0),
PINMUX_IPSR_GPSR(IP0SR1_11_8, A2),
PINMUX_IPSR_GPSR(IP0SR1_15_12, HRTS0_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, RTS0_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, A3),
PINMUX_IPSR_GPSR(IP0SR1_19_16, HCTS0_N),
PINMUX_IPSR_GPSR(IP0SR1_19_16, CTS0_N),
PINMUX_IPSR_GPSR(IP0SR1_19_16, A4),
PINMUX_IPSR_GPSR(IP0SR1_23_20, HTX0),
PINMUX_IPSR_GPSR(IP0SR1_23_20, TX0),
PINMUX_IPSR_GPSR(IP0SR1_23_20, A5),
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_RXD),
PINMUX_IPSR_GPSR(IP0SR1_27_24, DU_DR2),
PINMUX_IPSR_GPSR(IP0SR1_27_24, A6),
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP0SR1_31_28, DU_DR3),
PINMUX_IPSR_GPSR(IP0SR1_31_28, A7),
/* IP1SR1 */
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP1SR1_3_0, DU_DR4),
PINMUX_IPSR_GPSR(IP1SR1_3_0, A8),
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP1SR1_7_4, DU_DR5),
PINMUX_IPSR_GPSR(IP1SR1_7_4, A9),
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SS1),
PINMUX_IPSR_GPSR(IP1SR1_11_8, DU_DR6),
PINMUX_IPSR_GPSR(IP1SR1_11_8, A10),
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_SS2),
PINMUX_IPSR_GPSR(IP1SR1_15_12, DU_DR7),
PINMUX_IPSR_GPSR(IP1SR1_15_12, A11),
PINMUX_IPSR_GPSR(IP1SR1_19_16, MSIOF1_RXD),
PINMUX_IPSR_GPSR(IP1SR1_19_16, DU_DG2),
PINMUX_IPSR_GPSR(IP1SR1_19_16, A12),
PINMUX_IPSR_GPSR(IP1SR1_23_20, MSIOF1_TXD),
PINMUX_IPSR_GPSR(IP1SR1_23_20, HRX3),
PINMUX_IPSR_GPSR(IP1SR1_23_20, SCK3),
PINMUX_IPSR_GPSR(IP1SR1_23_20, DU_DG3),
PINMUX_IPSR_GPSR(IP1SR1_23_20, A13),
PINMUX_IPSR_GPSR(IP1SR1_27_24, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP1SR1_27_24, HSCK3),
PINMUX_IPSR_GPSR(IP1SR1_27_24, CTS3_N),
PINMUX_IPSR_GPSR(IP1SR1_27_24, DU_DG4),
PINMUX_IPSR_GPSR(IP1SR1_27_24, A14),
PINMUX_IPSR_GPSR(IP1SR1_31_28, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP1SR1_31_28, HRTS3_N),
PINMUX_IPSR_GPSR(IP1SR1_31_28, RTS3_N),
PINMUX_IPSR_GPSR(IP1SR1_31_28, DU_DG5),
PINMUX_IPSR_GPSR(IP1SR1_31_28, A15),
/* IP2SR1 */
PINMUX_IPSR_GPSR(IP2SR1_3_0, MSIOF1_SS1),
PINMUX_IPSR_GPSR(IP2SR1_3_0, HCTS3_N),
PINMUX_IPSR_GPSR(IP2SR1_3_0, RX3),
PINMUX_IPSR_GPSR(IP2SR1_3_0, DU_DG6),
PINMUX_IPSR_GPSR(IP2SR1_3_0, A16),
PINMUX_IPSR_GPSR(IP2SR1_7_4, MSIOF1_SS2),
PINMUX_IPSR_GPSR(IP2SR1_7_4, HTX3),
PINMUX_IPSR_GPSR(IP2SR1_7_4, TX3),
PINMUX_IPSR_GPSR(IP2SR1_7_4, DU_DG7),
PINMUX_IPSR_GPSR(IP2SR1_7_4, A17),
PINMUX_IPSR_GPSR(IP2SR1_11_8, MSIOF2_RXD),
PINMUX_IPSR_GPSR(IP2SR1_11_8, HSCK1),
PINMUX_IPSR_GPSR(IP2SR1_11_8, SCK1),
PINMUX_IPSR_GPSR(IP2SR1_11_8, DU_DB2),
PINMUX_IPSR_GPSR(IP2SR1_11_8, A18),
PINMUX_IPSR_GPSR(IP2SR1_15_12, MSIOF2_TXD),
PINMUX_IPSR_GPSR(IP2SR1_15_12, HCTS1_N),
PINMUX_IPSR_GPSR(IP2SR1_15_12, CTS1_N),
PINMUX_IPSR_GPSR(IP2SR1_15_12, DU_DB3),
PINMUX_IPSR_GPSR(IP2SR1_15_12, A19),
PINMUX_IPSR_GPSR(IP2SR1_19_16, MSIOF2_SCK),
PINMUX_IPSR_GPSR(IP2SR1_19_16, HRTS1_N),
PINMUX_IPSR_GPSR(IP2SR1_19_16, RTS1_N),
PINMUX_IPSR_GPSR(IP2SR1_19_16, DU_DB4),
PINMUX_IPSR_GPSR(IP2SR1_19_16, A20),
PINMUX_IPSR_GPSR(IP2SR1_23_20, MSIOF2_SYNC),
PINMUX_IPSR_GPSR(IP2SR1_23_20, HRX1),
PINMUX_IPSR_GPSR(IP2SR1_23_20, RX1_A),
PINMUX_IPSR_GPSR(IP2SR1_23_20, DU_DB5),
PINMUX_IPSR_GPSR(IP2SR1_23_20, A21),
PINMUX_IPSR_GPSR(IP2SR1_27_24, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP2SR1_27_24, HTX1),
PINMUX_IPSR_GPSR(IP2SR1_27_24, TX1_A),
PINMUX_IPSR_GPSR(IP2SR1_27_24, DU_DB6),
PINMUX_IPSR_GPSR(IP2SR1_27_24, A22),
PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF2_SS2),
PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK1_B),
PINMUX_IPSR_GPSR(IP2SR1_31_28, DU_DB7),
PINMUX_IPSR_GPSR(IP2SR1_31_28, A23),
/* IP3SR1 */
PINMUX_IPSR_GPSR(IP3SR1_3_0, IRQ0),
PINMUX_IPSR_GPSR(IP3SR1_3_0, DU_DOTCLKOUT),
PINMUX_IPSR_GPSR(IP3SR1_3_0, A24),
PINMUX_IPSR_GPSR(IP3SR1_7_4, IRQ1),
PINMUX_IPSR_GPSR(IP3SR1_7_4, DU_HSYNC),
PINMUX_IPSR_GPSR(IP3SR1_7_4, A25),
PINMUX_IPSR_GPSR(IP3SR1_11_8, IRQ2),
PINMUX_IPSR_GPSR(IP3SR1_11_8, DU_VSYNC),
PINMUX_IPSR_GPSR(IP3SR1_11_8, CS1_N_A26),
PINMUX_IPSR_GPSR(IP3SR1_15_12, IRQ3),
PINMUX_IPSR_GPSR(IP3SR1_15_12, DU_ODDF_DISP_CDE),
PINMUX_IPSR_GPSR(IP3SR1_15_12, CS0_N),
PINMUX_IPSR_GPSR(IP3SR1_19_16, GP1_28),
PINMUX_IPSR_GPSR(IP3SR1_19_16, D0),
PINMUX_IPSR_GPSR(IP3SR1_23_20, GP1_29),
PINMUX_IPSR_GPSR(IP3SR1_23_20, D1),
PINMUX_IPSR_GPSR(IP3SR1_27_24, GP1_30),
PINMUX_IPSR_GPSR(IP3SR1_27_24, D2),
/* IP0SR2 */
PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKIN),
PINMUX_IPSR_GPSR(IP0SR2_3_0, IPC_CLKEN_IN),
PINMUX_IPSR_GPSR(IP0SR2_3_0, DU_DOTCLKIN),
PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKOUT),
PINMUX_IPSR_GPSR(IP0SR2_7_4, IPC_CLKEN_OUT),
/* GP2_02 = SCL0 */
PINMUX_IPSR_MSEL(IP0SR2_11_8, GP2_02, SEL_I2C0_0),
PINMUX_IPSR_MSEL(IP0SR2_11_8, D3, SEL_I2C0_0),
PINMUX_IPSR_PHYS(IP0SR2_11_8, SCL0, SEL_I2C0_3),
/* GP2_03 = SDA0 */
PINMUX_IPSR_MSEL(IP0SR2_15_12, GP2_03, SEL_I2C0_0),
PINMUX_IPSR_MSEL(IP0SR2_15_12, D4, SEL_I2C0_0),
PINMUX_IPSR_PHYS(IP0SR2_15_12, SDA0, SEL_I2C0_3),
/* GP2_04 = SCL1 */
PINMUX_IPSR_MSEL(IP0SR2_19_16, GP2_04, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR2_19_16, MSIOF4_RXD, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR2_19_16, D5, SEL_I2C1_0),
PINMUX_IPSR_PHYS(IP0SR2_19_16, SCL1, SEL_I2C1_3),
/* GP2_05 = SDA1 */
PINMUX_IPSR_MSEL(IP0SR2_23_20, GP2_05, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR2_23_20, HSCK2, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR2_23_20, MSIOF4_TXD, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR2_23_20, SCK4, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP0SR2_23_20, D6, SEL_I2C1_0),
PINMUX_IPSR_PHYS(IP0SR2_23_20, SDA1, SEL_I2C1_3),
/* GP2_06 = SCL2 */
PINMUX_IPSR_MSEL(IP0SR2_27_24, GP2_06, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_27_24, HCTS2_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_27_24, MSIOF4_SCK, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_27_24, CTS4_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_27_24, D7, SEL_I2C2_0),
PINMUX_IPSR_PHYS(IP0SR2_27_24, SCL2, SEL_I2C2_3),
/* GP2_07 = SDA2 */
PINMUX_IPSR_MSEL(IP0SR2_31_28, GP2_07, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, HRTS2_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, MSIOF4_SYNC, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, RTS4_N, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP0SR2_31_28, D8, SEL_I2C2_0),
PINMUX_IPSR_PHYS(IP0SR2_31_28, SDA2, SEL_I2C2_3),
/* GP2_08 = SCL3 */
PINMUX_IPSR_MSEL(IP1SR2_3_0, GP2_08, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_3_0, HRX2, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_3_0, MSIOF4_SS1, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_3_0, RX4, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_3_0, D9, SEL_I2C3_0),
PINMUX_IPSR_PHYS(IP1SR2_3_0, SCL3, SEL_I2C3_3),
/* GP2_09 = SDA3 */
PINMUX_IPSR_MSEL(IP1SR2_7_4, GP2_09, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_7_4, HTX2, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_7_4, MSIOF4_SS2, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_7_4, TX4, SEL_I2C3_0),
PINMUX_IPSR_MSEL(IP1SR2_7_4, D10, SEL_I2C3_0),
PINMUX_IPSR_PHYS(IP1SR2_7_4, SDA3, SEL_I2C3_3),
/* GP2_10 = SCL4 */
PINMUX_IPSR_MSEL(IP1SR2_11_8, GP2_10, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP1SR2_11_8, TCLK2_B, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP1SR2_11_8, MSIOF5_RXD, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP1SR2_11_8, D11, SEL_I2C4_0),
PINMUX_IPSR_PHYS(IP1SR2_11_8, SCL4, SEL_I2C4_3),
/* GP2_11 = SDA4 */
PINMUX_IPSR_MSEL(IP1SR2_15_12, GP2_11, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP1SR2_15_12, TCLK3, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP1SR2_15_12, MSIOF5_TXD, SEL_I2C4_0),
PINMUX_IPSR_MSEL(IP1SR2_15_12, D12, SEL_I2C4_0),
PINMUX_IPSR_PHYS(IP1SR2_15_12, SDA4, SEL_I2C4_3),
/* GP2_12 = SCL5 */
PINMUX_IPSR_MSEL(IP1SR2_19_16, GP2_12, SEL_I2C5_0),
PINMUX_IPSR_MSEL(IP1SR2_19_16, TCLK4, SEL_I2C5_0),
PINMUX_IPSR_MSEL(IP1SR2_19_16, MSIOF5_SCK, SEL_I2C5_0),
PINMUX_IPSR_MSEL(IP1SR2_19_16, D13, SEL_I2C5_0),
PINMUX_IPSR_PHYS(IP1SR2_19_16, SCL5, SEL_I2C5_3),
/* GP2_13 = SDA5 */
PINMUX_IPSR_MSEL(IP1SR2_23_20, GP2_13, SEL_I2C5_0),
PINMUX_IPSR_MSEL(IP1SR2_23_20, MSIOF5_SYNC, SEL_I2C5_0),
PINMUX_IPSR_MSEL(IP1SR2_23_20, D14, SEL_I2C5_0),
PINMUX_IPSR_PHYS(IP1SR2_23_20, SDA5, SEL_I2C5_3),
/* GP2_14 = SCL6 */
PINMUX_IPSR_MSEL(IP1SR2_27_24, GP2_14, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP1SR2_27_24, IRQ4, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP1SR2_27_24, MSIOF5_SS1, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP1SR2_27_24, D15, SEL_I2C6_0),
PINMUX_IPSR_PHYS(IP1SR2_27_24, SCL6, SEL_I2C6_3),
/* GP2_15 = SDA6 */
PINMUX_IPSR_MSEL(IP1SR2_31_28, GP2_15, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP1SR2_31_28, IRQ5, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP1SR2_31_28, MSIOF5_SS2, SEL_I2C6_0),
PINMUX_IPSR_MSEL(IP1SR2_31_28, CPG_CPCKOUT, SEL_I2C6_0),
PINMUX_IPSR_PHYS(IP1SR2_31_28, SDA6, SEL_I2C6_3),
/* IP2SR2 */
PINMUX_IPSR_GPSR(IP2SR2_3_0, FXR_TXDA_A),
PINMUX_IPSR_GPSR(IP2SR2_3_0, MSIOF3_SS1),
PINMUX_IPSR_GPSR(IP2SR2_7_4, RXDA_EXTFXR_A),
PINMUX_IPSR_GPSR(IP2SR2_7_4, MSIOF3_SS2),
PINMUX_IPSR_GPSR(IP2SR2_7_4, BS_N),
PINMUX_IPSR_GPSR(IP2SR2_11_8, FXR_TXDB),
PINMUX_IPSR_GPSR(IP2SR2_11_8, MSIOF3_RXD),
PINMUX_IPSR_GPSR(IP2SR2_11_8, RD_N),
PINMUX_IPSR_GPSR(IP2SR2_15_12, RXDB_EXTFXR),
PINMUX_IPSR_GPSR(IP2SR2_15_12, MSIOF3_TXD),
PINMUX_IPSR_GPSR(IP2SR2_15_12, WE0_N),
PINMUX_IPSR_GPSR(IP2SR2_19_16, CLK_EXTFXR),
PINMUX_IPSR_GPSR(IP2SR2_19_16, MSIOF3_SCK),
PINMUX_IPSR_GPSR(IP2SR2_19_16, WE1_N),
PINMUX_IPSR_GPSR(IP2SR2_23_20, TPU0TO0),
PINMUX_IPSR_GPSR(IP2SR2_23_20, MSIOF3_SYNC),
PINMUX_IPSR_GPSR(IP2SR2_23_20, RD_WR_N),
PINMUX_IPSR_GPSR(IP2SR2_27_24, TPU0TO1),
PINMUX_IPSR_GPSR(IP2SR2_27_24, CLKOUT),
PINMUX_IPSR_GPSR(IP2SR2_31_28, TCLK1_A),
PINMUX_IPSR_GPSR(IP2SR2_31_28, EX_WAIT0),
/* IP0SR3 */
PINMUX_IPSR_GPSR(IP0SR3_7_4, CANFD0_TX),
PINMUX_IPSR_GPSR(IP0SR3_7_4, FXR_TXDA_B),
PINMUX_IPSR_GPSR(IP0SR3_7_4, TX1_B),
PINMUX_IPSR_GPSR(IP0SR3_11_8, CANFD0_RX),
PINMUX_IPSR_GPSR(IP0SR3_11_8, RXDA_EXTFXR_B),
PINMUX_IPSR_GPSR(IP0SR3_11_8, RX1_B),
PINMUX_IPSR_GPSR(IP0SR3_23_20, CANFD2_TX),
PINMUX_IPSR_GPSR(IP0SR3_23_20, TPU0TO2),
PINMUX_IPSR_GPSR(IP0SR3_23_20, PWM0),
PINMUX_IPSR_GPSR(IP0SR3_27_24, CANFD2_RX),
PINMUX_IPSR_GPSR(IP0SR3_27_24, TPU0TO3),
PINMUX_IPSR_GPSR(IP0SR3_27_24, PWM1),
PINMUX_IPSR_GPSR(IP0SR3_31_28, CANFD3_TX),
PINMUX_IPSR_GPSR(IP0SR3_31_28, PWM2),
/* IP1SR3 */
PINMUX_IPSR_GPSR(IP1SR3_3_0, CANFD3_RX),
PINMUX_IPSR_GPSR(IP1SR3_3_0, PWM3),
PINMUX_IPSR_GPSR(IP1SR3_7_4, CANFD4_TX),
PINMUX_IPSR_GPSR(IP1SR3_7_4, PWM4),
PINMUX_IPSR_GPSR(IP1SR3_7_4, FXR_CLKOUT1),
PINMUX_IPSR_GPSR(IP1SR3_11_8, CANFD4_RX),
PINMUX_IPSR_GPSR(IP1SR3_11_8, FXR_CLKOUT2),
PINMUX_IPSR_GPSR(IP1SR3_15_12, CANFD5_TX),
PINMUX_IPSR_GPSR(IP1SR3_15_12, FXR_TXENA_N),
PINMUX_IPSR_GPSR(IP1SR3_19_16, CANFD5_RX),
PINMUX_IPSR_GPSR(IP1SR3_19_16, FXR_TXENB_N),
PINMUX_IPSR_GPSR(IP1SR3_23_20, CANFD6_TX),
PINMUX_IPSR_GPSR(IP1SR3_23_20, STPWT_EXTFXR),
/* IP0SR4 */
PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_RX_CTL),
PINMUX_IPSR_GPSR(IP0SR4_3_0, AVB0_MII_RX_DV),
PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_RXC),
PINMUX_IPSR_GPSR(IP0SR4_7_4, AVB0_MII_RXC),
PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_RD0),
PINMUX_IPSR_GPSR(IP0SR4_11_8, AVB0_MII_RD0),
PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_RD1),
PINMUX_IPSR_GPSR(IP0SR4_15_12, AVB0_MII_RD1),
PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_RD2),
PINMUX_IPSR_GPSR(IP0SR4_19_16, AVB0_MII_RD2),
PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_RD3),
PINMUX_IPSR_GPSR(IP0SR4_23_20, AVB0_MII_RD3),
PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_TX_CTL),
PINMUX_IPSR_GPSR(IP0SR4_27_24, AVB0_MII_TX_EN),
PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_TXC),
PINMUX_IPSR_GPSR(IP0SR4_31_28, AVB0_MII_TXC),
/* IP1SR4 */
PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_TD0),
PINMUX_IPSR_GPSR(IP1SR4_3_0, AVB0_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_TD1),
PINMUX_IPSR_GPSR(IP1SR4_7_4, AVB0_MII_TD1),
PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_TD2),
PINMUX_IPSR_GPSR(IP1SR4_11_8, AVB0_MII_TD2),
PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_TD3),
PINMUX_IPSR_GPSR(IP1SR4_15_12, AVB0_MII_TD3),
PINMUX_IPSR_GPSR(IP1SR4_19_16, AVB0_TXCREFCLK),
PINMUX_IPSR_GPSR(IP1SR4_23_20, AVB0_MDIO),
PINMUX_IPSR_GPSR(IP1SR4_27_24, AVB0_MDC),
PINMUX_IPSR_GPSR(IP1SR4_31_28, AVB0_MAGIC),
/* IP2SR4 */
PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_LINK),
PINMUX_IPSR_GPSR(IP2SR4_7_4, AVB0_MII_TX_ER),
PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP2SR4_11_8, AVB0_MII_RX_ER),
PINMUX_IPSR_GPSR(IP2SR4_11_8, CC5_OSCOUT),
PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP2SR4_15_12, AVB0_MII_CRS),
PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_AVTP_PPS),
PINMUX_IPSR_GPSR(IP2SR4_19_16, AVB0_MII_COL),
/* IP0SR5 */
PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB1_MII_RX_DV),
PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_RXC),
PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB1_MII_RXC),
PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_RD0),
PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB1_MII_RD0),
PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_RD1),
PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB1_MII_RD1),
PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_RD2),
PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB1_MII_RD2),
PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_RD3),
PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB1_MII_RD3),
PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_TX_CTL),
PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB1_MII_TX_EN),
PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_TXC),
PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB1_MII_TXC),
/* IP1SR5 */
PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_TD0),
PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB1_MII_TD0),
PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_TD1),
PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB1_MII_TD1),
PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_TD2),
PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB1_MII_TD2),
PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_TD3),
PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB1_MII_TD3),
PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB1_TXCREFCLK),
PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB1_MDIO),
PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB1_MDC),
PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB1_MAGIC),
/* IP2SR5 */
PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_LINK),
PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB1_MII_TX_ER),
PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB1_MII_RX_ER),
PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB1_MII_CRS),
PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_AVTP_PPS),
PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB1_MII_COL),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* - AVB0 ------------------------------------------------ */
static const unsigned int avb0_link_pins[] = {
/* AVB0_LINK */
RCAR_GP_PIN(4, 17),
};
static const unsigned int avb0_link_mux[] = {
AVB0_LINK_MARK,
};
static const unsigned int avb0_magic_pins[] = {
/* AVB0_MAGIC */
RCAR_GP_PIN(4, 15),
};
static const unsigned int avb0_magic_mux[] = {
AVB0_MAGIC_MARK,
};
static const unsigned int avb0_phy_int_pins[] = {
/* AVB0_PHY_INT */
RCAR_GP_PIN(4, 16),
};
static const unsigned int avb0_phy_int_mux[] = {
AVB0_PHY_INT_MARK,
};
static const unsigned int avb0_mdio_pins[] = {
/* AVB0_MDC, AVB0_MDIO */
RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
};
static const unsigned int avb0_mdio_mux[] = {
AVB0_MDC_MARK, AVB0_MDIO_MARK,
};
static const unsigned int avb0_rgmii_pins[] = {
/*
* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
* AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
*/
RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
};
static const unsigned int avb0_rgmii_mux[] = {
AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
};
static const unsigned int avb0_txcrefclk_pins[] = {
/* AVB0_TXCREFCLK */
RCAR_GP_PIN(4, 12),
};
static const unsigned int avb0_txcrefclk_mux[] = {
AVB0_TXCREFCLK_MARK,
};
static const unsigned int avb0_avtp_pps_pins[] = {
/* AVB0_AVTP_PPS */
RCAR_GP_PIN(4, 20),
};
static const unsigned int avb0_avtp_pps_mux[] = {
AVB0_AVTP_PPS_MARK,
};
static const unsigned int avb0_avtp_capture_pins[] = {
/* AVB0_AVTP_CAPTURE */
RCAR_GP_PIN(4, 19),
};
static const unsigned int avb0_avtp_capture_mux[] = {
AVB0_AVTP_CAPTURE_MARK,
};
static const unsigned int avb0_avtp_match_pins[] = {
/* AVB0_AVTP_MATCH */
RCAR_GP_PIN(4, 18),
};
static const unsigned int avb0_avtp_match_mux[] = {
AVB0_AVTP_MATCH_MARK,
};
/* - AVB1 ------------------------------------------------ */
static const unsigned int avb1_link_pins[] = {
/* AVB1_LINK */
RCAR_GP_PIN(5, 17),
};
static const unsigned int avb1_link_mux[] = {
AVB1_LINK_MARK,
};
static const unsigned int avb1_magic_pins[] = {
/* AVB1_MAGIC */
RCAR_GP_PIN(5, 15),
};
static const unsigned int avb1_magic_mux[] = {
AVB1_MAGIC_MARK,
};
static const unsigned int avb1_phy_int_pins[] = {
/* AVB1_PHY_INT */
RCAR_GP_PIN(5, 16),
};
static const unsigned int avb1_phy_int_mux[] = {
AVB1_PHY_INT_MARK,
};
static const unsigned int avb1_mdio_pins[] = {
/* AVB1_MDC, AVB1_MDIO */
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
};
static const unsigned int avb1_mdio_mux[] = {
AVB1_MDC_MARK, AVB1_MDIO_MARK,
};
static const unsigned int avb1_rgmii_pins[] = {
/*
* AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
* AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
*/
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
};
static const unsigned int avb1_rgmii_mux[] = {
AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
};
static const unsigned int avb1_txcrefclk_pins[] = {
/* AVB1_TXCREFCLK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int avb1_txcrefclk_mux[] = {
AVB1_TXCREFCLK_MARK,
};
static const unsigned int avb1_avtp_pps_pins[] = {
/* AVB1_AVTP_PPS */
RCAR_GP_PIN(5, 20),
};
static const unsigned int avb1_avtp_pps_mux[] = {
AVB1_AVTP_PPS_MARK,
};
static const unsigned int avb1_avtp_capture_pins[] = {
/* AVB1_AVTP_CAPTURE */
RCAR_GP_PIN(5, 19),
};
static const unsigned int avb1_avtp_capture_mux[] = {
AVB1_AVTP_CAPTURE_MARK,
};
static const unsigned int avb1_avtp_match_pins[] = {
/* AVB1_AVTP_MATCH */
RCAR_GP_PIN(5, 18),
};
static const unsigned int avb1_avtp_match_mux[] = {
AVB1_AVTP_MATCH_MARK,
};
/* - AVB2 ------------------------------------------------ */
static const unsigned int avb2_link_pins[] = {
/* AVB2_LINK */
RCAR_GP_PIN(6, 17),
};
static const unsigned int avb2_link_mux[] = {
AVB2_LINK_MARK,
};
static const unsigned int avb2_magic_pins[] = {
/* AVB2_MAGIC */
RCAR_GP_PIN(6, 15),
};
static const unsigned int avb2_magic_mux[] = {
AVB2_MAGIC_MARK,
};
static const unsigned int avb2_phy_int_pins[] = {
/* AVB2_PHY_INT */
RCAR_GP_PIN(6, 16),
};
static const unsigned int avb2_phy_int_mux[] = {
AVB2_PHY_INT_MARK,
};
static const unsigned int avb2_mdio_pins[] = {
/* AVB2_MDC, AVB2_MDIO */
RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
};
static const unsigned int avb2_mdio_mux[] = {
AVB2_MDC_MARK, AVB2_MDIO_MARK,
};
static const unsigned int avb2_rgmii_pins[] = {
/*
* AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
* AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
*/
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
};
static const unsigned int avb2_rgmii_mux[] = {
AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
};
static const unsigned int avb2_txcrefclk_pins[] = {
/* AVB2_TXCREFCLK */
RCAR_GP_PIN(6, 12),
};
static const unsigned int avb2_txcrefclk_mux[] = {
AVB2_TXCREFCLK_MARK,
};
static const unsigned int avb2_avtp_pps_pins[] = {
/* AVB2_AVTP_PPS */
RCAR_GP_PIN(6, 20),
};
static const unsigned int avb2_avtp_pps_mux[] = {
AVB2_AVTP_PPS_MARK,
};
static const unsigned int avb2_avtp_capture_pins[] = {
/* AVB2_AVTP_CAPTURE */
RCAR_GP_PIN(6, 19),
};
static const unsigned int avb2_avtp_capture_mux[] = {
AVB2_AVTP_CAPTURE_MARK,
};
static const unsigned int avb2_avtp_match_pins[] = {
/* AVB2_AVTP_MATCH */
RCAR_GP_PIN(6, 18),
};
static const unsigned int avb2_avtp_match_mux[] = {
AVB2_AVTP_MATCH_MARK,
};
/* - AVB3 ------------------------------------------------ */
static const unsigned int avb3_link_pins[] = {
/* AVB3_LINK */
RCAR_GP_PIN(7, 17),
};
static const unsigned int avb3_link_mux[] = {
AVB3_LINK_MARK,
};
static const unsigned int avb3_magic_pins[] = {
/* AVB3_MAGIC */
RCAR_GP_PIN(7, 15),
};
static const unsigned int avb3_magic_mux[] = {
AVB3_MAGIC_MARK,
};
static const unsigned int avb3_phy_int_pins[] = {
/* AVB3_PHY_INT */
RCAR_GP_PIN(7, 16),
};
static const unsigned int avb3_phy_int_mux[] = {
AVB3_PHY_INT_MARK,
};
static const unsigned int avb3_mdio_pins[] = {
/* AVB3_MDC, AVB3_MDIO */
RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
};
static const unsigned int avb3_mdio_mux[] = {
AVB3_MDC_MARK, AVB3_MDIO_MARK,
};
static const unsigned int avb3_rgmii_pins[] = {
/*
* AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
* AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
*/
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
};
static const unsigned int avb3_rgmii_mux[] = {
AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
};
static const unsigned int avb3_txcrefclk_pins[] = {
/* AVB3_TXCREFCLK */
RCAR_GP_PIN(7, 12),
};
static const unsigned int avb3_txcrefclk_mux[] = {
AVB3_TXCREFCLK_MARK,
};
static const unsigned int avb3_avtp_pps_pins[] = {
/* AVB3_AVTP_PPS */
RCAR_GP_PIN(7, 20),
};
static const unsigned int avb3_avtp_pps_mux[] = {
AVB3_AVTP_PPS_MARK,
};
static const unsigned int avb3_avtp_capture_pins[] = {
/* AVB3_AVTP_CAPTURE */
RCAR_GP_PIN(7, 19),
};
static const unsigned int avb3_avtp_capture_mux[] = {
AVB3_AVTP_CAPTURE_MARK,
};
static const unsigned int avb3_avtp_match_pins[] = {
/* AVB3_AVTP_MATCH */
RCAR_GP_PIN(7, 18),
};
static const unsigned int avb3_avtp_match_mux[] = {
AVB3_AVTP_MATCH_MARK,
};
/* - AVB4 ------------------------------------------------ */
static const unsigned int avb4_link_pins[] = {
/* AVB4_LINK */
RCAR_GP_PIN(8, 17),
};
static const unsigned int avb4_link_mux[] = {
AVB4_LINK_MARK,
};
static const unsigned int avb4_magic_pins[] = {
/* AVB4_MAGIC */
RCAR_GP_PIN(8, 15),
};
static const unsigned int avb4_magic_mux[] = {
AVB4_MAGIC_MARK,
};
static const unsigned int avb4_phy_int_pins[] = {
/* AVB4_PHY_INT */
RCAR_GP_PIN(8, 16),
};
static const unsigned int avb4_phy_int_mux[] = {
AVB4_PHY_INT_MARK,
};
static const unsigned int avb4_mdio_pins[] = {
/* AVB4_MDC, AVB4_MDIO */
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
};
static const unsigned int avb4_mdio_mux[] = {
AVB4_MDC_MARK, AVB4_MDIO_MARK,
};
static const unsigned int avb4_rgmii_pins[] = {
/*
* AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
* AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
*/
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
};
static const unsigned int avb4_rgmii_mux[] = {
AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
};
static const unsigned int avb4_txcrefclk_pins[] = {
/* AVB4_TXCREFCLK */
RCAR_GP_PIN(8, 12),
};
static const unsigned int avb4_txcrefclk_mux[] = {
AVB4_TXCREFCLK_MARK,
};
static const unsigned int avb4_avtp_pps_pins[] = {
/* AVB4_AVTP_PPS */
RCAR_GP_PIN(8, 20),
};
static const unsigned int avb4_avtp_pps_mux[] = {
AVB4_AVTP_PPS_MARK,
};
static const unsigned int avb4_avtp_capture_pins[] = {
/* AVB4_AVTP_CAPTURE */
RCAR_GP_PIN(8, 19),
};
static const unsigned int avb4_avtp_capture_mux[] = {
AVB4_AVTP_CAPTURE_MARK,
};
static const unsigned int avb4_avtp_match_pins[] = {
/* AVB4_AVTP_MATCH */
RCAR_GP_PIN(8, 18),
};
static const unsigned int avb4_avtp_match_mux[] = {
AVB4_AVTP_MATCH_MARK,
};
/* - AVB5 ------------------------------------------------ */
static const unsigned int avb5_link_pins[] = {
/* AVB5_LINK */
RCAR_GP_PIN(9, 17),
};
static const unsigned int avb5_link_mux[] = {
AVB5_LINK_MARK,
};
static const unsigned int avb5_magic_pins[] = {
/* AVB5_MAGIC */
RCAR_GP_PIN(9, 15),
};
static const unsigned int avb5_magic_mux[] = {
AVB5_MAGIC_MARK,
};
static const unsigned int avb5_phy_int_pins[] = {
/* AVB5_PHY_INT */
RCAR_GP_PIN(9, 16),
};
static const unsigned int avb5_phy_int_mux[] = {
AVB5_PHY_INT_MARK,
};
static const unsigned int avb5_mdio_pins[] = {
/* AVB5_MDC, AVB5_MDIO */
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
};
static const unsigned int avb5_mdio_mux[] = {
AVB5_MDC_MARK, AVB5_MDIO_MARK,
};
static const unsigned int avb5_rgmii_pins[] = {
/*
* AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
* AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
*/
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
};
static const unsigned int avb5_rgmii_mux[] = {
AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
};
static const unsigned int avb5_txcrefclk_pins[] = {
/* AVB5_TXCREFCLK */
RCAR_GP_PIN(9, 12),
};
static const unsigned int avb5_txcrefclk_mux[] = {
AVB5_TXCREFCLK_MARK,
};
static const unsigned int avb5_avtp_pps_pins[] = {
/* AVB5_AVTP_PPS */
RCAR_GP_PIN(9, 20),
};
static const unsigned int avb5_avtp_pps_mux[] = {
AVB5_AVTP_PPS_MARK,
};
static const unsigned int avb5_avtp_capture_pins[] = {
/* AVB5_AVTP_CAPTURE */
RCAR_GP_PIN(9, 19),
};
static const unsigned int avb5_avtp_capture_mux[] = {
AVB5_AVTP_CAPTURE_MARK,
};
static const unsigned int avb5_avtp_match_pins[] = {
/* AVB5_AVTP_MATCH */
RCAR_GP_PIN(9, 18),
};
static const unsigned int avb5_avtp_match_mux[] = {
AVB5_AVTP_MATCH_MARK,
};
/* - CANFD0 ----------------------------------------------------------------- */
static const unsigned int canfd0_data_pins[] = {
/* CANFD0_TX, CANFD0_RX */
RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
};
static const unsigned int canfd0_data_mux[] = {
CANFD0_TX_MARK, CANFD0_RX_MARK,
};
/* - CANFD1 ----------------------------------------------------------------- */
static const unsigned int canfd1_data_pins[] = {
/* CANFD1_TX, CANFD1_RX */
RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
};
static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
/* - CANFD2 ----------------------------------------------------------------- */
static const unsigned int canfd2_data_pins[] = {
/* CANFD2_TX, CANFD2_RX */
RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
};
static const unsigned int canfd2_data_mux[] = {
CANFD2_TX_MARK, CANFD2_RX_MARK,
};
/* - CANFD3 ----------------------------------------------------------------- */
static const unsigned int canfd3_data_pins[] = {
/* CANFD3_TX, CANFD3_RX */
RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
};
static const unsigned int canfd3_data_mux[] = {
CANFD3_TX_MARK, CANFD3_RX_MARK,
};
/* - CANFD4 ----------------------------------------------------------------- */
static const unsigned int canfd4_data_pins[] = {
/* CANFD4_TX, CANFD4_RX */
RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
};
static const unsigned int canfd4_data_mux[] = {
CANFD4_TX_MARK, CANFD4_RX_MARK,
};
/* - CANFD5 ----------------------------------------------------------------- */
static const unsigned int canfd5_data_pins[] = {
/* CANFD5_TX, CANFD5_RX */
RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
};
static const unsigned int canfd5_data_mux[] = {
CANFD5_TX_MARK, CANFD5_RX_MARK,
};
/* - CANFD6 ----------------------------------------------------------------- */
static const unsigned int canfd6_data_pins[] = {
/* CANFD6_TX, CANFD6_RX */
RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
};
static const unsigned int canfd6_data_mux[] = {
CANFD6_TX_MARK, CANFD6_RX_MARK,
};
/* - CANFD7 ----------------------------------------------------------------- */
static const unsigned int canfd7_data_pins[] = {
/* CANFD7_TX, CANFD7_RX */
RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
};
static const unsigned int canfd7_data_mux[] = {
CANFD7_TX_MARK, CANFD7_RX_MARK,
};
/* - CANFD Clock ------------------------------------------------------------ */
static const unsigned int can_clk_pins[] = {
/* CAN_CLK */
RCAR_GP_PIN(3, 0),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb888_pins[] = {
/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
};
static const unsigned int du_rgb888_mux[] = {
DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
};
static const unsigned int du_clk_out_pins[] = {
/* DU_DOTCLKOUT */
RCAR_GP_PIN(1, 24),
};
static const unsigned int du_clk_out_mux[] = {
DU_DOTCLKOUT_MARK,
};
static const unsigned int du_sync_pins[] = {
/* DU_HSYNC, DU_VSYNC */
RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
};
static const unsigned int du_sync_mux[] = {
DU_HSYNC_MARK, DU_VSYNC_MARK,
};
static const unsigned int du_oddf_pins[] = {
/* DU_EXODDF/DU_ODDF/DISP/CDE */
RCAR_GP_PIN(1, 27),
};
static const unsigned int du_oddf_mux